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ADV7401
COMPONENT VIDEO PROCESSING
DIGITAL VIDEO INPUT PORT
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Formats supported include 525i, 625i, 525p, 625p, 720p,
1080i, and many other HDTV formats
Automatic adjustments include gain (contrast) and offset
(brightness); manual adjustment controls are also
supported
Support for analog component YPrPb/RGB video formats
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Supports raw 8-bit CVBS data from digital tuner
Support for 24-bit RGB input data from DVI Rx chip,
output converted to YCrCb 4:2:2
Support for 24-bit 4:4:4, 16-bit 4:2:2 525i, 625i, 525p, 625p,
1080i, 720p, VGA to SXGA @ 60 Hz input data from
HDMI Rx chip, output converted to 16-bit 4:2:2 YCrCb
with embedded sync or with separate HS, VS, or CS
GENERAL FEATURES
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Any-to-any, 3 × 3 color space conversion matrix supports
YCrCb-to-RGB and RGB-to-YCrCb
Standard identification (STDI) enables system level
component format detection
Synchronization source polarity detector (SSPD) deter-
mines the source and polarity of the synchronization
signals that accompany the input video
Certified Macrovision copy protection detection on
component formats (525i, 625i, 525p, and 625p)
Free-run output mode provides stable timing when no
video input is present
Arbitrary pixel sampling support for nonstandard video
sources
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HS, VS, and FIELD output signals with programmable
position, polarity, and width
Programmable interrupt request output pin, INT, signals
SDP/CP status changes
Supports two I 2 C host port interfaces (control and VBI)
Low power consumption: 1.8 V digital core, 3.3 V analog
and digital I/O, low power power-down mode, and green
PC mode
Industrial temperature range (?40°C to +85°C)
(except ADV7401KSTZ-140)
140 MHz speed grade (ADV7401KST-140)
100-lead, 14 mm × 14 mm, Pb-free LQFP
RGB GRAPHICS PROCESSING
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140 MSPS conversion rate supports RGB input resolutions
up to 1280 × 1024 @ 75 Hz (SXGA ); ( 110 MSPS conversion
rate for ADV7401BSTZ-110); ( 80 MSPS conversion rate for
ADV7401BSTZ-80)
Automatic or manual clamp and gain controls for graphics
modes
Contrast and brightness controls
32-phase DLL allows optimum pixel clock sampling
Automatic detection of sync source and polarity by SSPD
block
Standard identification is enabled by STDI block
RGB can be color space converted to YCrCb and
decimated to a 4:2:2 format for video centric backend IC
interfacing
Data enable (DE) output signal supplied for direct
connection to HDMI/DVI Tx IC
Arbitrary pixel sampling support for nonstandard video
sources
Rev. B | Page 14 of 20
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